{"id":157,"date":"2025-10-21T14:12:30","date_gmt":"2025-10-21T14:12:30","guid":{"rendered":"https:\/\/ykim.synology.me\/wordpress\/?page_id=157"},"modified":"2026-03-24T12:47:34","modified_gmt":"2026-03-24T17:47:34","slug":"yield-ramp-up-and-product-success","status":"publish","type":"page","link":"https:\/\/ykim.synology.me\/wordpress\/job-capability__trashed\/yield-ramp-up-and-product-success\/","title":{"rendered":"Yield Modeling and Ramp-Up"},"content":{"rendered":"\n
y<\/mi>=<\/mo>e<\/mi>\u2212<\/mo>1<\/mn><\/mrow><\/msup><\/mstyle>\\large y=e^{-1}<\/annotation><\/semantics><\/math><\/div>\n\n\n\n
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My yield modeling began with the development of a yield\u2011aware SRAM bit\u2011cell design methodology and subsequently extended to logic chips. The yield of a given SRAM macro is primarily<\/strong> determined by device centering and variability, long-tail effects, excursions<\/strong>, and test conditions<\/strong>. These are the same for the Logic macro. Centering and variability are statistically characterized and modeled. Once the model accounts for defects arising from centering and variability, the remaining defect mechanisms can be identified quickly.<\/p>\n\n\n\n

SRAM yield ramp-up is based on an SRAM macro. It makes early-stage defects easy to identify. This is why yield ramp-up starts with the SRAM macro rather than with the Logic macro. Meanwhile, the Logic yield requires different logic macros depending on the defect stages.<\/p>\n\n\n\n

My yield ramp-up and management work were based on the SRAM yield model and focused on specification definition and control<\/strong>. I forecasted the macro yield, compared it with the wafer yield, and coordinated corrective actions with multiple stakeholders. I also developed documents to support stakeholder communication. These documents were Best-Known Method (BKM) management, Statistical Process Control (SPC), Cp\/Cpk analysis, priority-wise k control, Out-of-Control Action Plans (OCAP), and a comprehensive framework of target specifications\u2014including Module Target Spec (MTS), physical MTS (pMTS), elementary MTS (eMTS), Electrical Target Spec (ETS), Layout Target Spec (LTS), Yield Target Spec (YTS).<\/p>\n\n\n\n

For product yield ramp-up, the average, variance, and outliers of fabrication, device, and product parameters were monitored and improved through a feedback cycle spanning from detection to yield enhancement. These parameters included both hard defects and soft defects, which were out of control in process, device, and product performance. I used the code-defect reduction<\/strong> method. All defects were coded, and their resolution status was shared with the teams. I am confident that this process can be embedded into the software platform and carried forward as a technical foundation for future projects, enabling rapid ramp-up during the early stages of development.<\/p>\n\n\n\n

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Yield Modeling<\/h2>\n\n\n\n
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Yield Ramp-Up<\/h2>\n\n\n\n
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