Figure of Merit (FoM) in Semiconductor Foundry

In the semiconductor foundry industry, a Figure of Merit (FoM) is a standardized numerical value used to quantify the performance and efficiency of a manufacturing process or a specific device [1]. These metrics allow foundries and chip designers to determine if a new technology node—such as the transition from 5nm to 3nm—provides enough improvement to justify the massive research and manufacturing costs [2].

1. Process-Level FoM: The “PPA” Standard

For logic foundries, the most critical FoM is known as PPA (Power, Performance, and Area) [3]. This represents the “golden triangle” of chip design and is used to benchmark every new process generation.

• Power: Focuses on reducing both dynamic power (energy used during switching) and static leakage current, which is vital for mobile devices [4].
• Performance: Typically measured by the maximum clock frequency ($F_{max}$) or the speed at which transistors operate [3].
• Area: Refers to the physical density of transistors. Foundries strive for “scaling,” which allows more transistors to fit in the same square millimeter, reducing the cost per chip [2].

2. Device-Level Figures of Merit

Beyond the overall process, engineers use specific device-level FoMs to compare the physical capabilities of transistors, especially for power and radio frequency (RF) applications.

FoM Type	Key Metrics	Application
Baliga FoM (BFoM)	$\epsilon \cdot \mu \cdot E_c^3$	Used for Power Devices. It defines the material’s ability to handle high voltage with minimum resistance [5].
Gate Charge FoM	$R_{on} \times Q_g$	Used for Switching Efficiency. It balances electrical resistance against the energy needed to turn the device on/off [6].
Johnson’s FoM	$E_c \cdot v_s / 2\pi$	Used for RF/High-Speed. It evaluates how well a material can handle high power at very high frequencies [7].

3. The Role of DTCO in Foundry FoMs

Modern foundries utilize DTCO (Design-Technology Co-Optimization) to maximize these FoMs [8]. As traditional “shrinking” becomes harder due to the laws of physics, foundries change the device architecture itself to improve the FoM.

For example, the shift from FinFET to Gate-All-Around (GAA) transistors was driven by the need to maintain a high FoM for electrostatic control and power efficiency at nodes below 5nm [9].

References

1. What is a Figure of Merit? – Definition from Techopedia
2. How to Choose a Semiconductor Process Node? – AnySilicon
3. What is PPA in Silicon Chip Design? – Synopsys
4. Understanding Power, Performance & Area (PPA) in VLSI – MOSart Labs
5. Figures of Merit for Power Devices – ResearchGate
6. Figures of Merit in Power Design: A Reliable Benchmark? – All About Circuits
7. Johnson’s figure of merit – Wikipedia
8. Design Technology Co-Optimization (DTCO) Solutions – Synopsys
9. Process Technology – Logic Node | Foundry | Samsung Semiconductor Global

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