- Developed statistical yieldโaware models for the SRAM bitโcell and array, known as the Zโscore method, and built an HSPICE/Perl/Motifโbased simulator called Zimulator.
- Published a tutorial book on the yield-aware statistical SRAM bit-cell design method. A portion of it is included below.
- Presented my work on statistical SRAM bitโcell design technology at the 2008 VLSI Symposium Tutorial. The full slides are available below.
- Achieved earlyโstage yield rampโup, driven primarily by SRAMโmacro yield, and delivered recordโbreaking yield at Samsung Foundry.
- Investigated 3D transistor structures and SRAM cell architectures enabled by waferโbonding technology.
Statistical SRAM Design (SSD)
2008 VLSI Technology Short Course, June 16, 2008
2008 VLSI Technology Short Course Brochure
Small-Circuit Compact Modeling
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